AN-817 Taking Advantage of ECL Minimum-Skew Clock Drivers

Digital systems have tended from their inception toward incorporation of higher speed elements rather than architectural changes as the solution to the computational speed problem. One result of this has been mounting pressure on the semiconductor elements of these systems for higher speed and all that this implies. Not only the operating frequency and signal propagation delay but also the relative timing relationships of devices performing parallel tasks were challenged. As semiconductor process improvements pushed operating speeds higher, the evolution from individually-packaged to multiply-packaged gates helped reduce delay and speed differences among like devices. Even so, areas still existed where system designers demanded ever greater improvements in performance uniformity of digital logic elements. The synchronization signal generation system, often referred to as the clock system, is one area in need of such improvement.